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Difference between revisions of "Zero2/Hardware/GPIO"

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|- style="font-weight:bold; text-align:center; background-color:#F2F2F2;"
 
|- style="font-weight:bold; text-align:center; background-color:#F2F2F2;"
 
! GPIO number
 
! GPIO number
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! Function5
 
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! Function3
 
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| GPIOAO_0
 
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| GPIOAO_1
 
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| SPI_B_SS0
 
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| GPIOZ_0
 
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| GPIOZ_1
 
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| I2C_EE_M0_SCL
 
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| GPIOA_0
 
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| GPIOC_7
 
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| MCLK_0
 
| MCLK_0
 
| UART_AO_B_RX
 
| UART_AO_B_RX
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| IR_REMOTE_OUT
 
| GPIOAO_9
 
| GPIOAO_9
 
| style="background-color:#008000; color:#FFF;" | 37
 
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| GPIOA_5
 
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| GPIOZ_7
 
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Revision as of 09:04, 5 January 2022

 Radxa Zero 2 >  Hardware >  GPIO

General purpose input-output (GPIO) connector

Radxa Zero 2 has a 40-pin expansion header. Each pin is distinguished by color.

GPIO number Function5 Function4 Function3 Function2 Function1 Pin# Pin# Function1 Function2 Function3 Function4 Function5 GPIO number
+3.3V 1 2 +5.0V
I2C_EE_M3_SDA GPIOA_14 3 4 +5.0V
I2C_EE_M3_SCL IR_REMOTE_IN GPIOA_15 5 6 GND
PWM_D GPIOZ_2 7 8 GPIOAO_0 UART_AO_A_TX
GND 9 10 GPIOAO_1 UART_AO_A_RX
GPIOZ_3 11 12 GPIOA_1
GPIOZ_4 13 14 GND
GPIOZ_5 15 16 NC
+3.3V 17 18 GPIOZ_6
SPI_B_MOSI UART_EE_C_RTS GPIOH_4 19 20 GND
PWM_F SPI_B_MISO UART_EE_C_CTS GPIOH_5 21 22 SARADC_CH3
PWM_B I2C_EE_M1_SCL SPI_B_SCLK UART_EE_C_TX GPIOH_7 23 24 GPIOH_6 UART_EE_C_RX SPI_B_SS0 I2C_EE_M1_SDA IR_REMOTE_OUT
GND 25 26 SARADC_CH2
PWM_B I2C_EE_M0_SDA GPIOZ_0 27 28 GPIOZ_1 I2C_EE_M0_SCL PWM_C
GPIOAO_7 29 30 GND
GPIOA_13 31 32 GPIOA_0 MCLK_0
UART_AO_B_TX GPIOAO_8 33 34 GND
GPIOA_2 35 36 GPIOC_7
MCLK_0 UART_AO_B_RX IR_REMOTE_OUT GPIOAO_9 37 38 GPIOA_5
GND 39 40 GPIOZ_7 I2C_EE_M0_SDA

More details about 40-pin Header

  • Pins marked with orange color are designed for debug console.
  • I2C: x3; I2C_EE_M1 (/dev/i2c-1), I2C_EE_M3 (/dev/i2c-3), I2C_AO_M0 (/dev/i2c-4)
  • PWM: x3; PWMAO_A, PWM_C
  • SPI: x2; SPI_A (/dev/spi0.0), SPI_B(/dev/spi1.0)
  • UART: x3; UART_AO_A (/dev/ttyAML0), UART_AO_B (/dev/ttyAML1), UART_EE_C (/dev/ttyAML4)
  • Pin#22 (GPIOC_7) and Pin#36 (GPIOH_8) are not available in the user space.

GPIO number

  • GPIOs are grouped in two banks, GPIO AO domain and GPIO EE domain
    • AO domain: GPIOAO_0 - GPIOAO_11
    • EE domain: GPIOA_14 - GPIOA_15 | GPIOH_0 - GPIOH_8 | GPIOX_0 - GPIOX_19
  • UARTs
    • AO domain: UARTAO_A | UARTAO_B
    • EE domain: UART_A | UART_B | UART_C
GPIO Chip
GPIO Name
Base Offset Formula
First GPIOAO_x 412 0-11 Base + Offset
First GPIOE_x 424 0-2 Base + Offset
Second GPIOZ_x 427 0-15 Base + Offset
Second GPIOH_x 443 0-8 Base + Offset
Second BOOT_x 452 0-15 Base + Offset
Second GPIOC_x 468 0-7 Base + Offset
Second GPIOA_x 476 0-15 Base + Offset
Second GPIOX_x 492 0-19 Base + Offset

Take GPIOX_10 as an example.

The base is 492 and the offset is 10. So the GPIOX_10's GPIO number is 492+10=502.