Difference between revisions of "Zero/hardware/gpio"

Latest revision as of 08:18, 7 November 2022

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 Radxa Zero >  Hardware >  GPIO

General purpose input-output (GPIO) connector

Radxa Zero has a 40-pin expansion header. Each pin is distinguished by color.

GPIO number	Function4	Function3	Function2	Function1	Pin#	Pin#	Function1	Function2	Function3	Function4	GPIO number
				+3.3V	1	2	+5.0V
490			I2C_EE_M3_SDA	GPIOA_14 (*)	3	4	+5.0V
491			I2C_EE_M3_SCL	GPIOA_15 (*)	5	6	GND
415	I2C_AO_S0_SDA	UART_AO_B_RX	I2C_AO_M0_SDA	GPIOAO_3	7	8	GPIOAO_0	UART_AO_A_TXD			412
				GND	9	10	GPIOAO_1	UART_AO_A_RXD			413
414	I2C_AO_S0_SCL	UART_AO_B_TX	I2C_AO_M0_SCL	GPIOAO_2	11	12	GPIOX_9	SPI_A_MISO	TDMA_D0		501
503	TDMA_SCLK	I2C_EE_M1_SCL	SPI_A_SCLK	GPIOX_11	13	14	GND
				SARADC_CH1	15	16	GPIOX_10	SPI_A_SS0	I2C_EE_M1_SDA	TDMA_FS	502
				+3.3V	17	18	GPIOX_8	SPI_A_MOSI	PWM_C	TDMA_D1	500
447		SPI_B_MOSI	UART_EE_C_RTS	GPIOH_4	19	20	GND
448	PWM_F	SPI_B_MISO	UART_EE_C_CTS	GPIOH_5	21	22	GPIOC_7	-			475
450	I2C_EE_M1_SCL	SPI_B_SCLK	UART_EE_C_TX	GPIOH_7	23	24	GPIOH_6	UART_EE_C_RX	SPI_B_SS0	I2C_EE_M1_SDA	449
				GND	25	26	SARADC_CH2
415	I2C_AO_S0_SDA	UART_AO_B_RX	I2C_AO_M0_SDA	GPIOAO_3	27	28	GPIOAO_2	I2C_AO_M0_SCL	UART_AO_B_TX	I2C_AO_S0_SCL	414
				NC	29	30	GND
				NC	31	32	GPIOAO_4	PWMAO_C			416
				NC	33	34	GND
420			UART_AO_B_TX	GPIOAO_8 available in v1.51 and later	35	36	GPIOH_8	-			451
421			UART_AO_B_RX	GPIOAO_9	37	38	GPIOAO_10 available up to v1.5	PWMAO_D			422
				GND	39	40	GPIOAO_11	PWMAO_A			423

Important note about Pin 35 and Pin 38

Depending on your hardware revision, one of the pin is connected to the Power LED, and is NOT connected on the 40-pin header. If your design uses those pins, please verify the hardware revision before purchasing.

More details about 40-pin Header

Pins marked with orange color are designed for debug console.
I2C: x3; I2C_EE_M1 (/dev/i2c-1), I2C_EE_M3 (/dev/i2c-3), I2C_AO_M0 (/dev/i2c-4)
(*) I2C_EE_M3 / GPIOA_14 & GPIOA_15 are connected to pull up resistors and the USB-C controller so cannot be used for general GPIO
PWM: x3; PWMAO_A, PWM_C
SPI: x2; SPI_A (/dev/spi0.0), SPI_B(/dev/spi1.0)
UART: x3; UART_AO_A (/dev/ttyAML0), UART_AO_B (/dev/ttyAML1), UART_EE_C (/dev/ttyAML4)
Pin#22 (GPIOC_7) and Pin#36 (GPIOH_8) are open drain pins. This means for input they need to connected to either GND or VCC (floating state is undefined), for output they will need external pull up. Additionally GPIOH_8 runs on 5V logic.

GPIO number

GPIOs are grouped in two banks, GPIO AO domain and GPIO EE domain
- AO domain: GPIOAO_0 - GPIOAO_11
- EE domain: GPIOA_14 - GPIOA_15 | GPIOH_0 - GPIOH_8 | GPIOX_0 - GPIOX_19
UARTs
- AO domain: UARTAO_A | UARTAO_B
- EE domain: UART_A | UART_B | UART_C

GPIO Chip	GPIO Name	Base	Offset	Formula
First	GPIOAO_x	412	0-11	Base + Offset
First	GPIOE_x	424	0-2	Base + Offset
Second	GPIOZ_x	427	0-15	Base + Offset
Second	GPIOH_x	443	0-8	Base + Offset
Second	BOOT_x	452	0-15	Base + Offset
Second	GPIOC_x	468	0-7	Base + Offset
Second	GPIOA_x	476	0-15	Base + Offset
Second	GPIOX_x	492	0-19	Base + Offset

Take GPIOX_10 as an example.

The base is 492 and the offset is 10. So the GPIOX_10's GPIO number is 492+10=502.

@@ Line 267: / Line 267: @@
 |
 | UART_AO_B_TX
-| <b>GPIOAO_8 (available in 1.51 and later)</b>
+| <b>GPIOAO_8
+available in v1.51 and later</b>
 | style="background-color:#008000; color:#FFF;" | 35
 |
@@ Line 285: / Line 286: @@
 |
 | style="background-color:#008000; color:#FFF;" | 38
-| <b>GPIOAO_10 (available up to 1.5)</b>
+| <b>GPIOAO_10
+available up to v1.5</b>
 | PWMAO_D
 |