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Difference between revisions of "Zero/hardware/gpio"

< Zero‎ | hardware
 
(17 intermediate revisions by 4 users not shown)
Line 5: Line 5:
 
  [[Zero | Radxa Zero]] > [[zero/hardware | Hardware]] > [[zero/hardware/gpio | GPIO]]
 
  [[Zero | Radxa Zero]] > [[zero/hardware | Hardware]] > [[zero/hardware/gpio | GPIO]]
  
 +
== <span id="gpio">General purpose input-output (GPIO) connector</span> ==
 +
 +
Radxa Zero has a 40-pin expansion header. Each pin is distinguished by color.
  
 
{| class="wikitable" style="vertical-align:middle; background-color:#F9F9F9;"
 
{| class="wikitable" style="vertical-align:middle; background-color:#F9F9F9;"
Line 36: Line 39:
 
|  
 
|  
 
|-
 
|-
 +
| 490
 
|  
 
|  
 
|  
 
|  
−
|  
+
| I2C_EE_M3_SDA
−
| I2CEE_SDA_M3
+
| GPIOA_14 (*)
−
| GPIOA_14
+
 
| style="background-color:#008000; color:#FFF;" | 3
 
| style="background-color:#008000; color:#FFF;" | 3
 
|  
 
|  
Line 50: Line 53:
 
|  
 
|  
 
|-
 
|-
 +
| 491
 
|  
 
|  
 
|  
 
|  
−
|  
+
| I2C_EE_M3_SCL
−
| I2CEE_SCL_M3
+
| GPIOA_15 (*)
−
| GPIOA_15
+
 
| style="background-color:#008000; color:#FFF;" | 5
 
| style="background-color:#008000; color:#FFF;" | 5
 
|  
 
|  
−
| style="background-color:#000000; color:#FFF;" | 6
+
| style="background-color:#000; color:#FFF" | 6
 
| GND
 
| GND
 
|  
 
|  
Line 64: Line 67:
 
|  
 
|  
 
|-
 
|-
−
|  
+
| 415
−
|  
+
| I2C_AO_S0_SDA
−
| UARTAO_B_TX
+
| UART_AO_B_RX
−
| I2CAO_SCL_M0
+
| I2C_AO_M0_SDA
 
| GPIOAO_3
 
| GPIOAO_3
 
| style="background-color:#008000; color:#FFF;" | 7
 
| style="background-color:#008000; color:#FFF;" | 7
Line 73: Line 76:
 
| style="background-color:#008000; color:#FFF;" | 8
 
| style="background-color:#008000; color:#FFF;" | 8
 
| GPIOAO_0
 
| GPIOAO_0
−
| style="background-color:#FFA500;" | UARTAO_A_TXD
+
| style="background-color:#FFA500;" | UART_AO_A_TXD
−
|
+
 
|  
 
|  
 
|  
 
|  
 +
| 412
 
|-
 
|-
 
|  
 
|  
Line 83: Line 86:
 
|  
 
|  
 
| GND
 
| GND
−
| style="background-color:#000000; color:#FFF;" | 9
+
| style="background-color:#000; color:#FFF" | 9
 
|  
 
|  
 
| style="background-color:#008000; color:#FFF;" | 10
 
| style="background-color:#008000; color:#FFF;" | 10
 
| GPIOAO_1
 
| GPIOAO_1
−
| style="background-color:#FFA500;" | UARTAO_A_RXD
+
| style="background-color:#FFA500;" | UART_AO_A_RXD
−
|
+
 
|  
 
|  
 
|  
 
|  
 +
| 413
 
|-
 
|-
−
|  
+
| 414
−
|  
+
| I2C_AO_S0_SCL
−
| UARTAO_B_RX
+
| UART_AO_B_TX
−
| I2CAO_SDA_M0
+
| I2C_AO_M0_SCL
 
| GPIOAO_2
 
| GPIOAO_2
 
| style="background-color:#008000; color:#FFF;" | 11
 
| style="background-color:#008000; color:#FFF;" | 11
Line 101: Line 104:
 
| style="background-color:#008000; color:#FFF;" | 12
 
| style="background-color:#008000; color:#FFF;" | 12
 
| GPIOX_9
 
| GPIOX_9
−
| SPIA_MISO
+
| SPI_A_MISO
−
|
+
| TDMA_D0
−
|  
+
 
|  
 
|  
 +
| 501
 
|-
 
|-
−
|  
+
| 503
−
|  
+
| TDMA_SCLK
−
| I2C_EE_SCL_M1
+
| I2C_EE_M1_SCL
−
| SPIA_SCLK
+
| SPI_A_SCLK
−
| GPIOX11
+
| GPIOX_11
 
| style="background-color:#008000; color:#FFF;" | 13
 
| style="background-color:#008000; color:#FFF;" | 13
 
|  
 
|  
−
| style="background-color:#000000; color:#FFF;" | 14
+
| style="background-color:#000; color:#FFF" | 14
 
| GND
 
| GND
 
|  
 
|  
Line 124: Line 127:
 
|  
 
|  
 
|  
 
|  
−
| ADC1
+
| SARADC_CH1
 
| style="background-color:#008000; color:#FFF;" | 15
 
| style="background-color:#008000; color:#FFF;" | 15
 
|  
 
|  
 
| style="background-color:#008000; color:#FFF;" | 16
 
| style="background-color:#008000; color:#FFF;" | 16
 
| GPIOX_10
 
| GPIOX_10
−
| SPIA_SS0
+
| SPI_A_SS0
−
| I2C_EE_SDA_M1
+
| I2C_EE_M1_SDA
−
|  
+
| TDMA_FS
−
|  
+
| 502
 
|-
 
|-
 
|  
 
|  
Line 143: Line 146:
 
| style="background-color:#008000; color:#FFF;" | 18
 
| style="background-color:#008000; color:#FFF;" | 18
 
| GPIOX_8
 
| GPIOX_8
−
| SPIA_MOSI
+
| SPI_A_MOSI
−
| PWMC
+
| PWM_C
−
|  
+
| TDMA_D1
−
|  
+
| 500
 
|-
 
|-
 +
| 447
 
|  
 
|  
−
|  
+
| SPI_B_MOSI
−
| SPIB_MOSI
+
| UART_EE_C_RTS
−
| UARTEE_C_RTS
+
 
| GPIOH_4
 
| GPIOH_4
 
| style="background-color:#008000; color:#FFF;" | 19
 
| style="background-color:#008000; color:#FFF;" | 19
 
|  
 
|  
−
| style="background-color:#000000; color:#FFF;" | 20
+
| style="background-color:#000; color:#FFF" | 20
 
| GND
 
| GND
 
|  
 
|  
Line 162: Line 165:
 
|  
 
|  
 
|-
 
|-
−
|  
+
| 448
−
| PWMF
+
| PWM_F
−
| SPIB_MISO
+
| SPI_B_MISO
−
| UARTEE_C_CTS
+
| UART_EE_C_CTS
 
| GPIOH_5
 
| GPIOH_5
 
| style="background-color:#008000; color:#FFF;" | 21
 
| style="background-color:#008000; color:#FFF;" | 21
Line 174: Line 177:
 
|  
 
|  
 
|  
 
|  
−
|  
+
| 475
 
|-
 
|-
−
|  
+
| 450
−
|  
+
| I2C_EE_M1_SCL
−
| SPIB_SCLK
+
| SPI_B_SCLK
−
| UARTEE_C_TX
+
| UART_EE_C_TX
 
| GPIOH_7
 
| GPIOH_7
 
| style="background-color:#008000; color:#FFF;" | 23
 
| style="background-color:#008000; color:#FFF;" | 23
Line 185: Line 188:
 
| style="background-color:#008000; color:#FFF;" | 24
 
| style="background-color:#008000; color:#FFF;" | 24
 
| GPIOH_6
 
| GPIOH_6
−
| UARTEE_C_RX
+
| UART_EE_C_RX
−
| SPIB_SS0
+
| SPI_B_SS0
−
|  
+
| I2C_EE_M1_SDA
−
|  
+
| 449
 
|-
 
|-
 
|  
 
|  
Line 195: Line 198:
 
|  
 
|  
 
| GND
 
| GND
−
| style="background-color:#000000; color:#FFF;" | 25
+
| style="background-color:#000; color:#FFF" | 25
 
|  
 
|  
 
| style="background-color:#008000; color:#FFF;" | 26
 
| style="background-color:#008000; color:#FFF;" | 26
−
| ADC2
+
| SARADC_CH2
 
|  
 
|  
 
|  
 
|  
Line 204: Line 207:
 
|  
 
|  
 
|-
 
|-
−
|  
+
| 415
−
|  
+
| I2C_AO_S0_SDA
−
| UARTAO_B_TX
+
| UART_AO_B_RX
−
| I2CAO_SCL
+
| I2C_AO_M0_SDA
 
| GPIOAO_3
 
| GPIOAO_3
 
| style="background-color:#00F; color:#FFF;" | 27
 
| style="background-color:#00F; color:#FFF;" | 27
Line 213: Line 216:
 
| style="background-color:#00F; color:#FFF;" | 28
 
| style="background-color:#00F; color:#FFF;" | 28
 
| GPIOAO_2
 
| GPIOAO_2
−
| I2CAO_SDA
+
| I2C_AO_M0_SCL
−
| UARTAO_B_RX
+
| UART_AO_B_TX
−
|  
+
| I2C_AO_S0_SCL
−
|  
+
| 414
 
|-
 
|-
 
|  
 
|  
Line 225: Line 228:
 
| style="background-color:#008000; color:#FFF;" | 29
 
| style="background-color:#008000; color:#FFF;" | 29
 
|  
 
|  
−
| style="background-color:#000000; color:#FFF;" | 30
+
| style="background-color:#000; color:#FFF" | 30
 
| GND
 
| GND
 
|  
 
|  
Line 244: Line 247:
 
|  
 
|  
 
|  
 
|  
−
|  
+
| 416
 
|-
 
|-
 
|  
 
|  
Line 253: Line 256:
 
| style="background-color:#008000; color:#FFF;" | 33
 
| style="background-color:#008000; color:#FFF;" | 33
 
|  
 
|  
−
| style="background-color:#000000; color:#FFF;" | 34
+
| style="background-color:#000; color:#FFF" | 34
 
| GND
 
| GND
 
|  
 
|  
Line 260: Line 263:
 
|  
 
|  
 
|-
 
|-
 +
| 420
 
|  
 
|  
 
|  
 
|  
−
| UARTAO_B_TX
+
| UART_AO_B_TX
−
| TDMB_SCLK
+
| <b>GPIOAO_8
−
| GPIOAO_8
+
available in v1.51 and later</b>
 
| style="background-color:#008000; color:#FFF;" | 35
 
| style="background-color:#008000; color:#FFF;" | 35
 
|  
 
|  
Line 272: Line 276:
 
|  
 
|  
 
|  
 
|  
−
|  
+
| 451
 
|-
 
|-
 +
| 421
 
|  
 
|  
 
|  
 
|  
−
| UARTAO_B_RX
+
| UART_AO_B_RX
−
| MCLK0
+
 
| GPIOAO_9
 
| GPIOAO_9
 
| style="background-color:#008000; color:#FFF;" | 37
 
| style="background-color:#008000; color:#FFF;" | 37
 
|  
 
|  
 
| style="background-color:#008000; color:#FFF;" | 38
 
| style="background-color:#008000; color:#FFF;" | 38
−
| GPIOAO_10
+
| <b>GPIOAO_10
−
| TDMB_D1
+
available up to v1.5</b>
−
|  
+
| PWMAO_D
 
|  
 
|  
 
|  
 
|  
 +
| 422
 
|-
 
|-
 
|  
 
|  
Line 293: Line 298:
 
|  
 
|  
 
| GND
 
| GND
−
| style="background-color:#000000; color:#FFF;" | 39
+
| style="background-color:#000; color:#FFF" | 39
 
|  
 
|  
 
| style="background-color:#008000; color:#FFF;" | 40
 
| style="background-color:#008000; color:#FFF;" | 40
Line 300: Line 305:
 
|  
 
|  
 
|  
 
|  
−
|  
+
| 423
 
|}
 
|}
  
−
== GPIO number ==
+
=== Important note about Pin 35 and Pin 38 ===
−
* GPIO are in two banks, GPIO AO domain and GPIO EE domain
+
 
 +
Depending on your [[Zero/hardware/revisions|hardware revision]], one of the pin is connected to the Power LED, and is <b>NOT</b> connected on the 40-pin header. If your design uses those pins, please verify the hardware revision before purchasing.
 +
 
 +
=== More details about 40-pin Header ===
 +
* Pins marked with orange color are designed for debug console.
 +
* I2C: x3; I2C_EE_M1 (/dev/i2c-1), I2C_EE_M3 (/dev/i2c-3), I2C_AO_M0 (/dev/i2c-4)
 +
* (*) I2C_EE_M3 / GPIOA_14 & GPIOA_15 are connected to pull up resistors and the USB-C controller so cannot be used for general GPIO
 +
* PWM: x3; PWMAO_A, PWM_C
 +
* SPI: x2; SPI_A (/dev/spi0.0), SPI_B(/dev/spi1.0)
 +
* UART: x3; UART_AO_A (/dev/ttyAML0), UART_AO_B (/dev/ttyAML1), UART_EE_C (/dev/ttyAML4)
 +
* Pin#22 (GPIOC_7) and Pin#36 (GPIOH_8) are open drain pins. This means for input they need to connected to either GND or VCC (floating state is undefined), for output they will need external pull up. Additionally GPIOH_8 runs on 5V logic.
 +
 
 +
=== GPIO number ===
 +
* GPIOs are grouped in two banks, GPIO AO domain and GPIO EE domain
 
** AO domain: GPIOAO_0 - GPIOAO_11
 
** AO domain: GPIOAO_0 - GPIOAO_11
 
** EE domain: GPIOA_14 - GPIOA_15 | GPIOH_0 - GPIOH_8 | GPIOX_0 - GPIOX_19  
 
** EE domain: GPIOA_14 - GPIOA_15 | GPIOH_0 - GPIOH_8 | GPIOX_0 - GPIOX_19  
Line 310: Line 328:
 
** AO domain: UARTAO_A | UARTAO_B
 
** AO domain: UARTAO_A | UARTAO_B
 
** EE domain: UART_A | UART_B | UART_C
 
** EE domain: UART_A | UART_B | UART_C
 +
 +
{| class="wikitable"
 +
|-
 +
! GPIO Chip<br />
 +
! GPIO Name<br />
 +
! Base
 +
! Offset
 +
! Formula
 +
|-
 +
| First
 +
| GPIOAO_x
 +
| 412
 +
| 0-11
 +
| Base + Offset
 +
|-
 +
| First
 +
| GPIOE_x
 +
| 424
 +
| 0-2
 +
| Base + Offset
 +
|-
 +
| Second
 +
| GPIOZ_x
 +
| 427
 +
| 0-15
 +
| Base + Offset
 +
|-
 +
| Second
 +
| GPIOH_x
 +
| 443
 +
| 0-8
 +
| Base + Offset
 +
|-
 +
| Second
 +
| BOOT_x
 +
| 452
 +
| 0-15
 +
| Base + Offset
 +
|-
 +
| Second
 +
| GPIOC_x
 +
| 468
 +
| 0-7
 +
| Base + Offset
 +
|-
 +
| Second
 +
| GPIOA_x
 +
| 476
 +
| 0-15
 +
| Base + Offset
 +
|-
 +
| Second
 +
| GPIOX_x
 +
| 492
 +
| 0-19
 +
| Base + Offset
 +
|}
 +
 +
Take GPIOX_10 as an example.
 +
 +
The base is 492 and the offset is 10. So the GPIOX_10's GPIO number is 492+10=502.

Latest revision as of 08:18, 7 November 2022

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 Radxa Zero >  Hardware >  GPIO

General purpose input-output (GPIO) connector

Radxa Zero has a 40-pin expansion header. Each pin is distinguished by color.

GPIO number Function4 Function3 Function2 Function1 Pin# Pin# Function1 Function2 Function3 Function4 GPIO number
+3.3V 1 2 +5.0V
490 I2C_EE_M3_SDA GPIOA_14 (*) 3 4 +5.0V
491 I2C_EE_M3_SCL GPIOA_15 (*) 5 6 GND
415 I2C_AO_S0_SDA UART_AO_B_RX I2C_AO_M0_SDA GPIOAO_3 7 8 GPIOAO_0 UART_AO_A_TXD 412
GND 9 10 GPIOAO_1 UART_AO_A_RXD 413
414 I2C_AO_S0_SCL UART_AO_B_TX I2C_AO_M0_SCL GPIOAO_2 11 12 GPIOX_9 SPI_A_MISO TDMA_D0 501
503 TDMA_SCLK I2C_EE_M1_SCL SPI_A_SCLK GPIOX_11 13 14 GND
SARADC_CH1 15 16 GPIOX_10 SPI_A_SS0 I2C_EE_M1_SDA TDMA_FS 502
+3.3V 17 18 GPIOX_8 SPI_A_MOSI PWM_C TDMA_D1 500
447 SPI_B_MOSI UART_EE_C_RTS GPIOH_4 19 20 GND
448 PWM_F SPI_B_MISO UART_EE_C_CTS GPIOH_5 21 22 GPIOC_7 - 475
450 I2C_EE_M1_SCL SPI_B_SCLK UART_EE_C_TX GPIOH_7 23 24 GPIOH_6 UART_EE_C_RX SPI_B_SS0 I2C_EE_M1_SDA 449
GND 25 26 SARADC_CH2
415 I2C_AO_S0_SDA UART_AO_B_RX I2C_AO_M0_SDA GPIOAO_3 27 28 GPIOAO_2 I2C_AO_M0_SCL UART_AO_B_TX I2C_AO_S0_SCL 414
NC 29 30 GND
NC 31 32 GPIOAO_4 PWMAO_C 416
NC 33 34 GND
420 UART_AO_B_TX GPIOAO_8

available in v1.51 and later

35 36 GPIOH_8 - 451
421 UART_AO_B_RX GPIOAO_9 37 38 GPIOAO_10

available up to v1.5

PWMAO_D 422
GND 39 40 GPIOAO_11 PWMAO_A 423

Important note about Pin 35 and Pin 38

Depending on your hardware revision, one of the pin is connected to the Power LED, and is NOT connected on the 40-pin header. If your design uses those pins, please verify the hardware revision before purchasing.

More details about 40-pin Header

  • Pins marked with orange color are designed for debug console.
  • I2C: x3; I2C_EE_M1 (/dev/i2c-1), I2C_EE_M3 (/dev/i2c-3), I2C_AO_M0 (/dev/i2c-4)
  • (*) I2C_EE_M3 / GPIOA_14 & GPIOA_15 are connected to pull up resistors and the USB-C controller so cannot be used for general GPIO
  • PWM: x3; PWMAO_A, PWM_C
  • SPI: x2; SPI_A (/dev/spi0.0), SPI_B(/dev/spi1.0)
  • UART: x3; UART_AO_A (/dev/ttyAML0), UART_AO_B (/dev/ttyAML1), UART_EE_C (/dev/ttyAML4)
  • Pin#22 (GPIOC_7) and Pin#36 (GPIOH_8) are open drain pins. This means for input they need to connected to either GND or VCC (floating state is undefined), for output they will need external pull up. Additionally GPIOH_8 runs on 5V logic.

GPIO number

  • GPIOs are grouped in two banks, GPIO AO domain and GPIO EE domain
    • AO domain: GPIOAO_0 - GPIOAO_11
    • EE domain: GPIOA_14 - GPIOA_15 | GPIOH_0 - GPIOH_8 | GPIOX_0 - GPIOX_19
  • UARTs
    • AO domain: UARTAO_A | UARTAO_B
    • EE domain: UART_A | UART_B | UART_C
GPIO Chip
 GPIO Name
 Base Offset Formula
First GPIOAO_x 412 0-11 Base + Offset
First GPIOE_x 424 0-2 Base + Offset
Second GPIOZ_x 427 0-15 Base + Offset
Second GPIOH_x 443 0-8 Base + Offset
Second BOOT_x 452 0-15 Base + Offset
Second GPIOC_x 468 0-7 Base + Offset
Second GPIOA_x 476 0-15 Base + Offset
Second GPIOX_x 492 0-19 Base + Offset

Take GPIOX_10 as an example.

The base is 492 and the offset is 10. So the GPIOX_10's GPIO number is 492+10=502.

Retrieved from "https://wiki.radxa.com/mw/index.php?title=Zero/hardware/gpio&oldid=8949"