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Difference between revisions of "Zero2/Hardware/GPIO"

(More details about 40-pin Header)
 
(11 intermediate revisions by 2 users not shown)
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! Function4
 
! Function4
 
! Function5
 
! Function5
 +
! Function6
 
! GPIO number
 
! GPIO number
 
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| 490
 
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| +5.0V
 
| +5.0V
 
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| 429
 
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| TDMC_DIN0
 
| TDMC_DIN0
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| 412
 
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| style="background-color:#008000; color:#FFF;" | 15
 
| style="background-color:#008000; color:#FFF;" | 15
 
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| style="background-color:#808000; color:#FFF;" | 16
+
| style="background-color:#008000; color:#FFF;" | 16
| NC
+
| GPIOZ_8
|  
+
| ETH_RGMII_TX_CLK
|  
+
| BT656_A_DIN4
|  
+
| TSIN_B_DIN2
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| MCLK_1
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| I2C_EE_M0_SCL
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| 435
 
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| 448
 
| TDMB_DIN3
 
| TDMB_DIN3
 
| TDMB_D3
 
| TDMB_D3
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| style="background-color:#008000; color:#FFF;" | 22
 
| style="background-color:#008000; color:#FFF;" | 22
| SARADC_CH3
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| GPIOZ_9
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| ETH_TXEN
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| BT656_A_DIN5
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| TSIN_B_DIN3
 
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| 436
 
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| 450
 
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| PWM_B
 
| PWM_B
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| IR_REMOTE_OUT
 
| IR_REMOTE_OUT
 
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| 449
 
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| 427
 
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| I2C_EE_M0_SCL
 
| I2C_EE_M0_SCL
 
| PWM_C
 
| PWM_C
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| 428
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| 419
 
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| 480
 
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| PWM_D
|  
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| TDMB_DIN1
| TDMC_SLV_FS
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| TDMB_D1
| TDMC_FS
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| GPIOA_4
| GPIOA_13
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| style="background-color:#008000; color:#FFF;" | 31
 
| style="background-color:#008000; color:#FFF;" | 31
 
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| TDMB_SLV_SCLK
 
| TDMB_SLV_SCLK
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| 478
 
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| style="background-color:#008000; color:#FFF;" | 36
 
| style="background-color:#008000; color:#FFF;" | 36
| GPIOC_7
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| GPIOA_3
| PCIECK_REQN
+
| TDMB_D0
| WORLD_SYNC
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| TDMB_DIN0
 
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| 479
 
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| 421
 
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| MCLK_0
 
| MCLK_0
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| 481
 
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| TDMC_SLV_SCLK
 
| TDMC_SLV_SCLK
 
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|434
 
|}
 
|}
  
 
=== More details about 40-pin Header ===
 
=== More details about 40-pin Header ===
 +
 +
The device number listed below is for reference only. Depending on how many devices you have enabled the number for each can change.
  
 
I2C devices (3)
 
I2C devices (3)
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* I2C_EE_M1 (/dev/i2c-1)
 
* I2C_EE_M1 (/dev/i2c-1)
 
* I2C_EE_M3 (/dev/i2c-3)
 
* I2C_EE_M3 (/dev/i2c-3)
 +
 +
I2S device (1)
 +
* TDMB
  
 
PWM devices (4)
 
PWM devices (4)
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* PWM_F (/sys/class/pwm/pwmchip2/pwm1)
 
* PWM_F (/sys/class/pwm/pwmchip2/pwm1)
  
To use PWM_C and PWM_D together, please use <code>meson-g12b-pwm-c-d-gpioz-1-2</code> overlay instead of individual overlays. In this case PWM_D will be available at <code>/sys/class/pwm/pwmchip1/pwm1</code>.
+
To use PWM_C and PWM_D together, please use <code>meson-g12b-pwm-c-d-gpioz-1-2</code> overlay instead of individual overlays.
  
 
UART devices (3)
 
UART devices (3)
 
* UART_AO_A (/dev/ttyAML0)
 
* UART_AO_A (/dev/ttyAML0)
* UART_AO_B (/dev/ttyAML1)
+
* UART_AO_B (/dev/ttyAML6)
* UART_EE_C (/dev/ttyAML4)
+
* UART_EE_C (/dev/ttyAML7)
 +
if you  enable UART_AO_B only or only enable UART_EE_C, the UART device is /dev/ttyAML6, if you enable UART_AO_B and UART_EE_C at the same time,
 +
the device of UART_AO_B is /dev/ttyAML6, and UART_EE_C is /dev/ttyAML7
  
 
SPI device (1)
 
SPI device (1)
* SPI_B (/dev/spidev1.0)
+
* SPI_B (/dev/spidev0.0)
  
 
=== GPIO number ===
 
=== GPIO number ===

Latest revision as of 03:20, 17 November 2022

 Radxa Zero 2 >  Hardware >  GPIO

General purpose input-output (GPIO) connector

Radxa Zero 2 has a 40-pin expansion header. Each pin is distinguished by color.

GPIO number Function6 Function5 Function4 Function3 Function2 Function1 Pin# Pin# Function1 Function2 Function3 Function4 Function5 Function6 GPIO number
+3.3V 1 2 +5.0V
490 I2C_EE_M3_SDA WORLD_SYNC GPIOA_14 3 4 +5.0V
491 I2C_EE_M3_SCL IR_REMOTE_IN GPIOA_15 5 6 GND
429 TDMC_DIN0 TDMC_D0 TSIN_B_VALID PWM_D GPIOZ_2 7 8 GPIOAO_0 UART_AO_A_TX 412
GND 9 10 GPIOAO_1 UART_AO_A_RX 413
430 TDMC_DIN1 TDMC_D1 TSIN_B_SOP GPIOZ_3 11 12 GPIOA_1 TDMB_SCLK TDMB_SLV_SCLK 477
431 TDMC_DIN2 TDMC_D2 TSIN_B_DIN0 GPIOZ_4 13 14 GND
432 TDMC_DIN3 TDMC_D3 TSIN_B_CLK GPIOZ_5 15 16 GPIOZ_8 ETH_RGMII_TX_CLK BT656_A_DIN4 TSIN_B_DIN2 MCLK_1 I2C_EE_M0_SCL 435
+3.3V 17 18 GPIOZ_6 TSIN_B_FAIL TDMC_FS TDMC_SLV_FS 433
447 SPI_B_MOSI UART_EE_C_RTS GPIOH_4 19 20 GND
448 TDMB_DIN3 TDMB_D3 PWM_F SPI_B_MISO UART_EE_C_CTS GPIOH_5 21 22 GPIOZ_9 ETH_TXEN BT656_A_DIN5 TSIN_B_DIN3 436
450 PWM_B I2C_EE_M1_SCL SPI_B_SCLK UART_EE_C_TX GPIOH_7 23 24 GPIOH_6 UART_EE_C_RX SPI_B_SS0 I2C_EE_M1_SDA IR_REMOTE_OUT 449
GND 25 26 SARADC_CH2
427 PWM_B I2C_EE_M0_SDA GPIOZ_0 27 28 GPIOZ_1 I2C_EE_M0_SCL PWM_C 428
419 TDMB_SLV_FS TDMB_FS TSIN_A_DIN0 GPIOAO_7 29 30 GND
480 PWM_D TDMB_DIN1 TDMB_D1 GPIOA_4 31 32 GPIOA_0 MCLK_0 476
420 TDMB_SLV_SCLK TDMB_SCLK TSIN_A_CLK UART_AO_B_TX GPIOAO_8 33 34 GND
478 TDMB_SLV_FS TDMB_FS GPIOA_2 35 36 GPIOA_3 TDMB_D0 TDMB_DIN0 479
421 MCLK_0 TSIN_A_VALID UART_AO_B_RX IR_REMOTE_OUT GPIOAO_9 37 38 GPIOA_5 PDM_DIN3 TDMB_DIN2 TDMB_D2 481
GND 39 40 GPIOZ_7 I2C_EE_M0_SDA TSIN_B_DIN1 TDMC_SCLK TDMC_SLV_SCLK 434

More details about 40-pin Header

The device number listed below is for reference only. Depending on how many devices you have enabled the number for each can change.

I2C devices (3)

  • I2C_EE_M0 (/dev/i2c-0)
  • I2C_EE_M1 (/dev/i2c-1)
  • I2C_EE_M3 (/dev/i2c-3)

I2S device (1)

  • TDMB

PWM devices (4)

  • PWM_B (/sys/class/pwm/pwmchip6/pwm1)
  • PWM_C (/sys/class/pwm/pwmchip4/pwm0)
  • PWM_D (/sys/class/pwm/pwmchip4/pwm1)
  • PWM_F (/sys/class/pwm/pwmchip2/pwm1)

To use PWM_C and PWM_D together, please use meson-g12b-pwm-c-d-gpioz-1-2 overlay instead of individual overlays.

UART devices (3)

  • UART_AO_A (/dev/ttyAML0)
  • UART_AO_B (/dev/ttyAML6)
  • UART_EE_C (/dev/ttyAML7)

if you enable UART_AO_B only or only enable UART_EE_C, the UART device is /dev/ttyAML6, if you enable UART_AO_B and UART_EE_C at the same time, the device of UART_AO_B is /dev/ttyAML6, and UART_EE_C is /dev/ttyAML7

SPI device (1)

  • SPI_B (/dev/spidev0.0)

GPIO number

GPIO Chip
GPIO Name
Base Offset Formula
First GPIOAO_x 412 0-11 Base + Offset
First GPIOE_x 424 0-2 Base + Offset
Second GPIOZ_x 427 0-15 Base + Offset
Second GPIOH_x 443 0-8 Base + Offset
Second BOOT_x 452 0-15 Base + Offset
Second GPIOC_x 468 0-7 Base + Offset
Second GPIOA_x 476 0-15 Base + Offset
Second GPIOX_x 492 0-19 Base + Offset

Take GPIOX_10 as an example.

The base is 492 and the offset is 10. So the GPIOX_10's GPIO number is 492+10=502.

We recommend you to use gpiod and libmraa, which support accessing GPIO pins by 40-pin header number, instead of SoC defined GPIO number.